Response Electronics CL6011B Dokumentacja Pobierz pdf (Strona 41)

3Ć21 Theory of Operation: Point Processing

Original Ć June 1990 CE4.2:CL6211

3.3.3.1.2 Set Point Limiting

The set point limiting function is used to restrict the upper and lower

limits of a DCP's set point, and prevent that set point from moving

outside of the range established by a configured high and low set point

limit. If a new set point is entered for the DCP, and that value exceeds

the set point high limit, then the set point is set to that limit, and the SP

High (SPHI) alarm bit is set to a value of 1. If the new set point is less

than the set point low limit, then the set point is set equal to that limit,

and the SP Low (SPLO) alarm bit is set to 1. The SPHI and SPLO alarm

bits allow for operator indication at the console that either high or low set

point limiting has occurred. Set point limiting is available on all PCAs

except the high/low signal selector.

3.3.3.1.3 Set Point Velocity Limiting

All Primary Control Algorithms except Manual Loader, Signal Selector,

and Bias and Gain support a feature called SP Velocity Limiting". This

configuration choice enables a tuning parameter which is then used to

limit the maximum rate of change of the SP value used by the PCA,

internally. Effectively, this limits the allowable change that the operator

can make to the operating point of the process when in the Automatic

control mode.

Note that the SP Velocity Limiting will limit the internal SP value, which is

not displayed to the operator. The user simply selects the desired SP,

and the PCA then limits the results of the operator change accordingly.

Since the SP Velocity Limiting only limits the internal SP value used by

the PCA, the FST function SPLD (Set Point Load) will load the SP value

selected by the operator, and the SVA output of the SPLD FST function

will not reflect the velocity limited SP used by the PCA.

3.3.3.1.4 Transfer Bias Ramping

Bumpless transfers from the manual mode to the automatic mode on

bias & gain and P/PD PCAs are achieved by either an internal transfer

bias or a backward calculated DCP bias. Transfer bias ramping allows

the normal DCP bias value to be maintained during a mode transfer. If it

is not enabled, the normal DCP bias value is changed during the mode

transfer and must be reset after the transfer has been completed.

When transfer bias ramping is enabled, the internal transfer bias value is

back calculated to achieve a bumpless mode transfer. For example, if

the IVP was 60% while the DCP was in manual mode, and the IVP should

be 50% after the switch to automatic mode, the transfer bias value will be

set to 10%.

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Response Electronics CL6011B Dokumentacja Strona 41